Design Specifications

The specifications and requirements for this design will be listed here for easy access.

=General Specifications=
 * Harvard architecture (separate data and instruction memory)
 * Data memory is 16 bits wide, 64K deep
 * Instruction memory is 20 (24?) bits wide, 48K deep
 * Instruction memory not writable under normal operation
 * 256 element deep return stack x 16 bits wide
 * 256 element deep data stack x 16 bits wide

=Instruction Set Specificaions= - -
 * ALU functions (all 16 bit operations):
 * Add / Subtract
 * AND / OR / XOR
 * INV / NEG / TEST
 * Instruction addressing modes (PC functions):
 * Immediate (16-bit target in opcode)
 * Computed (16-bit target in TOS)
 * RTS (16-bit target in TOR)
 * IP relative: immediate (16-bit offset in opcode)
 * IP relative: computed (16-bit offset in TOS)

-
 * Data addressing modes:
 * Immediate (16-bit target in opcode)
 * Computed (16-bit target in TOS)
 * Indirect/Immediate (16-bit address of target in opcode)
 * Indirect/Calculated (16-bit address of target in TOS)
 * Register Offset/Immediate (16-bit offset in opcode)
 * Register Offset/Computed (16-bit offset in TOS)
 * Status functions:
 * Bittest

=UI / Connection Specifications=
 * Alphanumeric keyboard input
 * Alphanumeric display output
 * Connections for external I/O expansion

=Debug Station Specifications=
 * Override memory access (all spaces)
 * Step / freerun through code segments