Addressing Modes

The ALU needs one or two sources for its operands. These inputs are typically drawn from different potential sources and latched into input buffers while the ALU operates on them. This particular design has an additional requirement in that it must allow "0-operand" functionality. What that means is the operands may be taken from the top two items in the parameter stack. This will be the default arrangement in this design but in order to accommodate other software models, it will also takes inputs from designated registers and data memory directly. These multiple (and conflicting) requirements require additional control circuitry in the ALU control section. The need for the ALU to operate fast puts even more strain on the design process.

This design will support advanced addressing modes.

Because this is a 16-bit design, there are no accommodations for 8-bit processing in the machine code. This eliminates the need for some addressing modes and even some instructions (e.g., "branch" -vs- "long branch").

- =Typical Addressing Modes=

General Modes
A list of addressing modes supported by a typical modern CPU follows:
 * Inherent - any parameter is included in the opcode, or no parameters are needed.
 * Immediate - the parameter itself is included in the instruction and follows the opcode.
 * Extended - the address of parameter follows the opcode in the instruction.
 * Extended Indirect - the address of the parameter's address follows the opcode.
 * Immediate IP Relative - compute (IP) + an offset (which follows the opcode in the instruction) as the target of a branch.
 * Indexed - the parameter (direct) or its address (indirect) use the value in an index (16b) register - using an offset:
 * Constant Offset - (IRx) + inline constant (2's comp) - immediate index
 * The IP may be used with a constant offset, in both direct and indirect.
 * ACC Offset - (IRx) + (ACC) (2's comp) - accumulator index
 * Autoinc/dec - uses (IRx) and incs or decs IRx (before/after use). No other offsets. This mode is typically used when the specified register functions as a stack pointer.

Branch/Jump addressing modes
The parameter used in these instructions becomes the address of the next instruction to execute. Program execution control is necessary in all but the most simple programs. An advanced set of conditional execution instructions (branches) is very useful for smooth program flow and execution speed. The execution control instructions come in two basic varieties: jumps and branches. Jumps are unconditional execution instructions and can use various addressing modes. Branches can be conditional or unconditional executions instructions but use only the instruction pointer (IP) relative (with immediate offset) addressing mode.

The jump (JMP) and jump to subroutine (JSR) instructions may use the following addressing modes:
 * Immediate - the target address follows the opcode
 * Extended - the target address is located at the address following the opcode
 * Indexed -

The branch (BRxx) and branch-to-subroutine (BSR) instructions use a single addressing mode: Branch instructions are a series of conditional execution instructions, except for Branch Always (BRA) and Branch to Subroutine (BSR). They test a specified bit in the status register and only branch if the condition is satisfied. Otherwise, the next instruction in line is executed and the branch is effectively a NOOP (no operation). BRA and BSR are like the JMP and JSR but use the IP-relative addressing mode.
 * Immediate IP Relative - an offset follows the opcode and is added to (IP) to get the new effective execution address.

In many CPUs another difference between the jump and branch instruction groups is in the post-opcode parameter. They may offer an 8-bit version of the branch instructions but only 16-bit versions of the jump instructions. Since this system does not use 8-bit data lengths, there are no 8-bit versions of these instructions.

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This design is quite different from the typical modern CPU in that it is parameter-stack based. It may also be called a "0-operand" system, meaning all operands are "popped" from the parameter stack and all results are automatically "pushed" there.