Character Display

The character display in the SC-CPU is a 4 line, 24 characters per line, 5x7 dot matrix display. It is intended for alpha-numeric display only.

It interfaces to the CPU through the I/O instructions and has an internal controller independant of the CPU.

There is a line buffer of 256 characters which the CPU can write to and read from. This buffer is used to hold all the character data needed by the display. The buffer is addressed either by the CPU interface or the display controller. When addressing the buffer, the controller uses a base address plus offset. The base address is held in a register that the CPU writes to (but cannot read it back) and represents the start of the current line. This will generally be different for each line of the display. The offset from this base address is generated by an internal counter.

Operation
The ROMs used to encode the display data from the character data act as latches. They hold the character data without any need to constantly refresh them. All lines use a single contoller and buffer RAM. The RAM is 256 cells (16 bits) deep so it can hold all the display and much more. The ROMS and therefore the display may be refreshed one line at a time. The controller or CPU writes to the base address register to set the beginning of a line, then the counter is incremented through the number of digits in the line and data at the effective address is written to the decoding ROMs for the current digit.

In IDLE or NORMAL mode, the character data has been all latched into the digit ROMs and nothing is getting updated. The CPU can access the buffer RAM and write new data for one character or the entire display without interferring with the actual display. The CPU also has the capability to read reandomly from the buffer RAM. When the controller is not busy, the CPU can signal it to perform a command. Usually the command is to refresh a particular line.
 * NORMAL MODE

To refresh a line, the controller first sets the 'BUSY' signal so the CPU can tell if the display RAM is available and resets the offset counter to '00'. The base address register is loaded with the proper value for the line being refreshed. These values are 'hardwired' into the controller. The controller then initiates a read from the RAM. At this point, the offset address is present on the internal digit address bus and the character data is present on the character data bus. The "Latch_Digit" signal is sent to the proper display line and that character data is latched at the proper digit. The counter is then incremented and if the counter value is not beyond the line limit, the buffer RAM is again read and the process repeats from that point.
 * REFRESH LINE

Once all digits in the current line have been written to the display, the 'BUSY' signal is cleared and the CPU may access the buffer RAM as needed. Since the display controller only operates in response to commands from the CPU, there is no need for the CPU to set a busy indicator for the controller to monitor.


 * CPU Commands

These commands or instructions are initiated by the CPU interface.
 * Write RAM - The address and data for a specific location in buffer RAM is output on the internal data bus (TOS) and the command is then sent to the controller.
 * Read RAM - The address for a specific location in buffer RAM is output on the internal data bus and the command is then sent to the controller which reads that location and outputs the data there onto the data bus. The CPU must remove any data before latching the data bus into TOS.
 * Refresh Line ## - For now, each line will have its own refresh command.
 * Set Base Address - latches address data from the internal data bus into the base address register.

Electric Design
DISPLAY MODULE

The display is made of 4-LEDs with 12 each per character. This provides a 6 by 8 dot matrix for each character. The leftmost column and topmost row are left blank by the character ROMs. The LEDs are driven by memory bank 'encoders' or the character ROMs, one per LED. These are controlled as latches. The address inputs specify the ASCII character and their internal codes define the character shape. The ROMs for one character are all latched by a common signal derived from the digit address presented to the display from the controller.

The latch signal for the digit ROMs comes from an address decoder followed by an AND gate. The AND is enabled by the "Latch_Digit" control signal. The data latched into the ROM and the address of the current digit come from the display controller.

DISPLAY CONTROLLER

The controller is comprised of a base address register, an offset counter, addition module, a line buffer RAM and the components needed to interface to the display and the CPU.

The base address register is a latch which may be set by either the CPU or the display controller and is one input to the adder module.

The offset counter is a simple, 8 bit counter that may also be controlled by either the CPU or the display controller. It recognizes the commands RESET and INCREMENT. Its output goes to the addition module and to the display (ROMs).

The base address register and the offset counter are the two inputs to the addition module. The output typically goes to the buffer RAM address inputs but it may be disabled so the CPU may control the buffer RAM address directly.

The buffer RAM holds the character data for the entire display, not just a single line. It may be read or written by the CPU and the display controller reads from it to create the final display.

Controls

 * Counter Control - Tells the offset counter what to do. The instructions are just increment and reset.
 * Base Reg Latch - latches the data from the CPU's internal data bus into the base register.
 * Digit Select Enable - This control is pulsed with the 'address' of the specific line where the digit address and data are to be written to. This will eventually pulse the latch control for the specific digit in the specific line as desired.
 * RAM Control - tells the buffer ram when to read or write.
 * Adder Output Enable - enables the output of the adder function to go to the buffer RAM address inputs. Except when the CPU is using the RAM, this will always be enabled.
 * Latch Digit - latches the current character data output from the display buffer into the display digit whose number is specified by the current counter output.
 * Data Out Enable - enables the connection from the RAM buffer data output to the CPU's internal data bus.
 * Latch Data In - latches the information coming in from the CPU's internal data bus. This info includes both the address within the RAM buffer and the data to be stored there. (This may be superfluous.) A WRITE will then be performed on the RAM to save this data. A READ can also be performed but the controller will have to latch '0000' before reading back the data. If this latch control is removed, then the latch of '0000' is not necessary.
 * Controller BUSY - this is not a signal to the display controller. However the controller must set it appropriately to avoid contention with the CPU. The CPU can read back this status bit.
 * End_Line - This is another signal that comes from the controller. It is set when the offset counter is incremented beond the limit of the display and it forces the sequencer to quit the refresh line command and enter the IDLE state.
 * End_Line - This is another signal that comes from the controller. It is set when the offset counter is incremented beond the limit of the display and it forces the sequencer to quit the refresh line command and enter the IDLE state.

Inputs / Outputs

 * RAM Address In Low, High - latched data from the CPU to define the location to store character data.
 * Data In Low, High - latched data from the CPU to be stored in the location specified by the RAM address.
 * Base Address Low, High - latched data from the CPU or controller to set the start of the current buffer space.
 * Char Address Out Low, High - selects the digit in the line to write data to
 * Digit Select Enable - allows to pulse the above address
 * Character Data Out Low, High - the data to be written at the location specified by the Char Address Out
 * Character Data Out Low, High - the data to be written at the location specified by the Char Address Out

Sequencing
- reset offset counter
 * REFRESH LINE

- set BASE_REGISTER to appropriate value for the current line

- set ADDER_OUTPUT_ENABLE line

- wait for adder?

- enter loop:

-- send read command to RAM  (gets character data from the proper location in the buffer)

-- send current row# to ROW_ENABL  (latches the character data into the display ROMs)

-- send '00' to ROW_ENABLE, send INC to COUNTER_CONTROL  (if limit is passed, this sequencer is aborted - 'F' is sent to command input)

-- wait (9 tics total) for counter, adder and compare  (before restarting loop)

-- send command to restart this loop