Instruction Fetch

The subsytem to fetch the next instruction to execute is composed of the Program Counter, the Return Stack and the Program ROM. These functional blocks are tightly tied together to give the fastest instruction fetch time as possible while providing the necessary functionality.

=Instruction Subsystem Requirements= The requirements of this subsystem are as follows:
 * Latch and hold the current Instruction Code (in the ICL) until the next instruction is available and the system is ready to process it. Cleanly latch the next instruction code when appropriate.
 * Automatically calculate the address of the next instruction in sequence (+1) and have it ready to latch into the IP when needed.
 * Take a value from the current instruction code to be used as the IP. This supports JMP and JSR IMMediate instructions.
 * PUSH the address of the next instruction in sequence ([IP]+1) to the Return Stack (TOR). This supports subroutine calls.
 * POP the Return Stack (TOR) to the IP. This supports subroutine returns.

- Connections to the data stack (TOS). Some or all of these might benefit by allowing the same access via a register!?!?!
 * Allow the system to pop TOS to IP. Supports complex addressing modes.
 * Allow the system to push the IP to TOS. Supports complex addressing modes.
 * Allow the system to push (a portion of) the ICL to TOS. Supports complex addressing modes.
 * Allow the system to push TOR to TOS. Supports temp use of the Return Stack for data.
 * Allow the system to pop TOS to TOR. Supports temp use of the Return Stack for data.

=Background Notes= Because the memory in the SC environment is dual ported, write-then-read and its output internally latched, we can do some functions in parallel provided the system connections do not preclude it. For example the Return Stack Pointer may be updated and a new value written into that location while the 'old' value is still available to be read at its output. (The new location must be explicitly read to the outputs.)

- The IP has several possible load sources: PC ALU (default), TOS, TOR and ICL. - The IP may be read to the TOS - The PC ALU output may be latched into the TOR
 * The Data Stack connects to several points in this subsystem. It can be popped into the IP or the TOR. It can be pushed with the IP, the TOR or (part of) the ICL.
 * 8 bits of the Instruction Code Latch (ICL) may be latched into the IP. This provides for redirection (jumps) in program execution. Such a redirection uses the immediate addressing mode because the target address is stored in the instruction.